The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, an extreme ultraviolet lithography (EUVL) is implemented to meet a need of a higher resolution lithography process. In processes of fabricating an extreme ultraviolet (EUV) mask, reflectivity of a border on the EUV mask raises challenges to produce an IC pattern on a wafer substrate.
Accordingly, what is needed is a method that addresses the above issue and continues to improve the semiconductor manufacture process in a wafer fab. Also what is need is an improved mask, such as can be used in EUVL.